The present invention relates to a charge-pump circuit formed on a silicon substrate, and particularly relates to a charge-pump circuit capable of being incorporated in a standard CMOS process LSI.
A charge-pump circuit of Cockcroft-Walton type capable of being formed on a silicon substrate is disclosed in “On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique,” by J. F. Dickson, IEEE J. Solid-State Circuits, Vol. SC-11, No. 3, pp. 374-378, June 1976. In this circuit, a booster cell of each stage is composed of a drive MOS transistor of which a drain and a gate are connected to each other and a capacitor, and a voltage of the preceding stage is superimposed on the succeeding booster cell sequentially according to two-phase clock signals to obtain a desired voltage in the booster cell at the final stage.
In the above Cockcroft-Walton charge-pump circuit, as the boosted potential becomes higher, the back bias effect becomes more significant and the threshold voltage of the drive transistor increases, thereby lowering the charge-pump efficiency.
Under the circumstances, U.S. Pat. No. 6,603,346 proposes a technique in which N-type well regions in which drive PMOS transistors are formed are isolated electrically from each other in a P-type silicon substrate and the substrate potential is fixed to the source potential of the drive PMOS transistor in each stage for minimizing the influence of the back bias effect.
Another technique disclosed in U.S. Pat. No. 6,121,821 refers to a case where a triple well structure is employed in a P-type silicon substrate, wherein P-type well regions in which drive NMOS transistors are formed are isolated electrically from each other, and the substrate potential is fixed to the drain potential of the drive NMOS transistor in each stage for minimizing the influence of the back bias effect. The patent introduces a charge-pump circuit of four-phase clock signal type, as well.
Referring to nonvolatile semiconductor memory devices, such as flash memories, EEPROMs, and the like, voltages higher than the power supply voltage is necessary for signal writing and signal erasure. In a flash memory, a high breakdown voltage transistor for withstanding high bias capable of being used in the charge-pump circuit can be fabricated in an exclusive process. In mounting the charge-pump circuit on an advanced standard CMOS process LSI, however, the exclusive process high breakdown voltage transistor cannot be used. Therefore, when each of the capacitors of the charge-pump circuit is composed of a single MOS transistor, a high voltage is applied between the gate and the substrate to cause problems that the breakdown voltage of the capacitor cannot be guaranteed because of time dependent dielectric breakdown (TDDB), and the like. This makes difficult to mount the charge-pump circuit on the advanced standard CMOS process LSI.
Further, electric isolation of the well regions in which the drive MOS transistors are formed as a countermeasure for minimizing the back bias effect necessitates isolation layers between the respective stages, involving an increase in layout area of the charge-pump circuit.